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esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 1/12 50ma ultra-low quiescent current ldo linear regulator general description the emp8046 is a positive voltage regulator with high accuracy output voltage and ultra-low quiescent current which is typically 1.0 a. the device is ideal for battery powered handheld equipments which require low quiescent current. the emp8046 contains a bandgap voltage reference, an error amplifier, a p-channel pass transistor, and a resistor-d ivider for setting output voltage. the output voltage is fixed with high accuracy by advanced trimming technology. the emp8046 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 1.0 f. the devices are available in sot-23-3 and sot-89-3 packages. applications g battery power equipments g portable communication devices g precision voltage references g hand-held electronics g wireless communication systems features g operating voltages range: 2.5v to 18v g maximum output current: 100ma g low dropout: 800mv @ 50ma g 2% output voltage tolerance g low esr capacitor compatible g rohs compliant and 100% lead(pb)-free and green (halogen free with commercial standard) typical application
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 2/12 connection diagrams order information emp8046-xxvb03nrr xx output voltage vb03 sot-23-3 package nrr rohs & halogen free package rating: -40 to 85c package in tape & reel emp8046-xxvg03nrr xx output voltage vg03 sot-89-3 package nrr rohs & halogen free package rating: -40 to 85c package in tape & reel order, marking and packing information package vout product id. marking packing 3.3v EMP8046-33VB03NRR sot-23-3 5.0v emp8046-50vb03nrr tape & reel 3kpcs 3.3v emp8046-33vg03nrr sot-89-3 5.0v emp8046-50vg03nrr tape & reel 1kpcs
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 3/12 pin functions name sot-23-3 sot-89-3 function gnd 1 1 ground pin v out 2 3 output voltage v in 3 2 supply voltage input require a minimum input capacitor around 1f to ensure stability and sufficient decoupling from the ground pin. functional block diagram v in v out r1 r2 gnd 1.23v bandgap reference current limit fig.1. functional block diagram of emp8046
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 4/12 absolute maximum ratings (notes 1, 2) v in -0.3v to 20v power dissipation (note 3) storage temperature range -65c to 150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec.) 260c operating ratings (note 1, 2) supply voltage 2.5v to 18v operating temperature range -40c to 85c thermal resistance ( ja , note 3)) 156c/w (sot-23-3) 101c/w (sot-89-3) thermal resistance ( jc , note 4)) 82c/w (sot-23-3) 54c/w (sot-89-3) electrical characteristics t a = 25c, v out (nom)=5v; unless otherwise specified, all limits guaranteed for v in = v out +1v, c in = c out =1f. symbol parameter conditions min typ (note 6) max units v in input voltage 2.5 18 v v in =v out +1.0v, i out =1ma, v out Q 2.6v v out * 0.976 v out * 1.024 v out output voltage v in =v out +1.0v, i out =1ma, v out R 2.7v v out * 0.98 v out v out * 1.02 v i out maximum output current average dc current rating 50 ma i limit output current limit 100 ma i out = 0ma 1.0 2.5 i q supply current i out = 50ma 1.0 2.5 a i out = 1ma 16 20 i out = 10ma 160 200 v do dropout voltage v out =5.0v (note. 7) i out = 50ma 800 1000 mv line regulation i out = 1ma, (v out + 1v) v in 12v 0.2 0.3 %/v v out load regulation 0.1ma i out 50ma 0.01 0.02 %/ma
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 5/12 note 1: absolute maximum ratings indicate limits beyond which damage may occur. note 2: all voltages are in respect to the potential of the ground pin. note 3: ja is measured in the natural convection at t a =25 on a high effectively thermal conductivity test board (2 layers, 2s0p). note 4: jc represents the resistance between the chip and the top of the package case. note 5: maximum power dissipation for the device is calculated using the following equation: ja a t - j(max) t d p = where t j (max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction-to-ambient thermal resistance. for example, for the sot-89-3 package ja =101c/w, t j (max)=150c and using t a =25c, the maximum power dissipation is 1.23w. the derating factor (-1/ ja )=-9.9mw/c. below 25c the power dissip ation figure can be increased by 9.9mw per degree and similarly decreased by this factor for temperatures above 25c. note 6: typical values represent the most typical parametric norm. note 7: dropout voltage is measured by reducing v in until v out drops to 98% of its nominal value.
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 6/12 typical performance characteristics unless otherwise specified, v in = v out (nom) + 1v, v out =5v, c in = c out = 1.0f, t a = 25c quiescent current vs. input voltage, i out =1ma quiescent current vs. input voltage, i out =50ma 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 6.0 9.0 12.0 15.0 18.0 vin (v) quiescent current (ua) 0.0 0.5 1.0 1.5 2.0 2.5 0.0 3.0 6.0 9.0 12.0 15.0 18.0 vin (v) q u iescen t c u rren t (u a ) output voltage vs. temperature, v in =12v quiescent current vs. temperature, v in =12v 4.85 4.90 4.95 5.00 5.05 5.10 5.15 -40 -15 10 35 60 85 temperat ure ('c) vout (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -40 -15 10 35 60 85 temperature ('c) quiescent current (ua) line transient, v in =5v to 6v, i out =50ma load transient, v in =5v, i out =1ma to 60ma
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 7/12 application information general description the emp8046 is a low quiescent current ldo linear regulator. it supplies a preset 5.0v output voltage for output current up to 50ma. other mask options for special output voltages from 1.5v to 5.0v with 100mv increment are also available. as illustrated in function block diagram, emp8046 consists of a 1.23v band gap reference, error amplifier, p-channel pass transistor and an internal fe edback voltage divider. the 1.23v band gap reference is connected to the error amplifier, which compares the band gap reference to the feedback voltage. afterwards, the error amplifier am plifies the voltage difference. if the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled lower. this allows more current to pass to the output pin and increases the output voltage. if the feedback voltage is too high, the pass-transistor gate is pulled up to decrease the output voltage. the output voltage is feedback through an internal resistor-divider connected to out. additional blocks include an output current limiter, thermal sensor, and shutdown logic. internal p-channel pass transistor the emp8046 features a p-channel mo sfet pass transistor. unlike similar designs using pnp pass transistors, p-channel mosfets require no base drive, which reduces ground pin current. pnp- ba sed regulators also waste considerable current in dropout condit ions when the pass transistor satura tes, and use high base-drive currents under large loads. the emp8046 does not experi ence these drawbacks and consumes only 1.0 a (typ.) of ground pin current under heavy loads as well as in dropout conditions. input-output voltage a regulator?s minimum input-output voltage differential, or dropout voltage, determines the lowest usable supply voltage. in battery-powered systems, this will determine the useful end-of -life battery voltage. the emp8046 uses a p-channel mosfet pass transistor, whos e dropout voltage is a function of drain-to-source on-resistance (r ds(on) ) multiplied by the load current. () out on ds out in dropout i r v v v = ? = input capacitor a minimum input capacitance of 1f is required for emp8046. the capacitor value may be increased without limit. improper workbench set-ups may have adverse effects on the normal operation of the regulator. one example is the instability that may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. this will esta blish a pseudo lcr network and is likely to happen under high current conditions or near dropout. a 10f tantalum input capacitor will dampen the parasitic lcr action due to its high esr. however, cautions should be exercised to avoid regulator short-circuit damage when tantalum capacitors are used since they are prone to fail in short-circuit operating conditions.
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 8/12 output capacitor the emp8046 is specially designed for use with ceramic output capacitors of as low as 1.0f to take advantage of the savings in cost and space as we ll as the superior filter ing of high frequency noise. capacitors of higher value or other types may be used, but it is important to make sure its equivalent series resistance (esr) is restricted to less than 0.5 ? . the use of larger capacitors with smaller esr values is desirable for applications involving large and fast input or output transients, as well as for situations where the application systems are not physically located immediately adjacent to the battery power source. typical ceramic capacitors suitable for use with the emp8046 are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10% , respectively, as the temperature increases. power dissipation an ic junction with a low thermal resistance is preferred because it is relatively effective in dissipating its thermal energy to its ambient, thus resulting in a re latively low and desirable junction temperature. the relationship between ja and t j is as follows: t j = ja x (p d ) + t a t a is the ambient temperature, and p d is the power generated by the ic and can be written as: p d = i out (v in - v out ) as the equations show, it is desirable to work with ics whose ja values are small so that t j does not increase strongly with p d . to avoid thermally overloading the emp8046, refrain from exceeding the absolute maximum junction temperature rating of 150c under continuous operating conditions. overstressing the regulator with high loading currents and elevated input-to-output differe ntial voltages can increase the ic die temperature significantly.
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 9/12 package outline drawing sot-23-3
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 10/12 package outline drawing sot-89-3 symbpls min. nom. max. a 1.40 1.60 b 0.44 0.56 b1 0.36 0.48 c 0.35 0.44 d 4.40 4.60 d1 1.35 1.83 e 2.29 2.60 h 3.94 4.25 e 1.50 bsc e1 3.00 bsc l 0.89 1.2 unit: mm
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 11/12 revision history revision date description 0.1 2010.09.12 original 0.2 2011.12.02 modify t he output voltage range.
esmt/emp preliminary emp8046 elite semiconductor memory technology inc./elite micropower inc. publication date : dec. 2011 revision : 0.2 12/12 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without th e prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt as sumes no responsibility for any error in this document, and reserves th e right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of ou r products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inherently a certain rate of failure. to minimize risks associat ed with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if prod ucts described here are to be used for such kinds of application, pu rchaser must do its own quality assurance testing appropriate to such applications.

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